A NAND flash memory includes a plurality of memory cell transistors, each having a laminated gate structure constituted by a floating gate and a control gate.
More specifically, the NAND flash memory includes a plurality of memory cell arrays. Each memory cell array includes a plurality of memory cell transistors connected to each other and selection gate transistors provided at both ends of the plurality of connected memory cell transistors. The plurality of memory cell transistors are arranged with a predetermined interval therebetween in a row direction in a cell array region of the NAND flash memory. Each Shallow Trench Isolation (STI) region is formed between every adjacent pair of memory cell transistors in the row direction. Each STI region is formed with a trench. A device isolation insulating film is embedded into each trench.
Further, the NAND flash memory includes not only the above cell array region but also a peripheral circuit region having a plurality of peripheral transistors. An STI region is formed between the peripheral circuit region and the cell array region. This STI region formed between the peripheral circuit region and the cell array region has a larger width than the STI region formed between every adjacent pair of memory cell transistors. A trench is formed in the STI region between the peripheral circuit region and the cell array region. A device isolation insulating film is embedded into this trench. Further, inter-gate insulating films are formed on this device isolation insulating film.
Nowadays, the NAND flash memories are required to have finer structures. Accordingly, the spaces between the memory cell transistors and the peripheral transistors are increasingly reduced.